In recent years, ceramic packaging modules with cavity die attach and gold wire bonding with PGA contacts have become increasingly popular as the single chip carriers for the I--486 family of microprocessors. Alumina is frequently the ceramic material chosen while molybdenum or tungsten is widely used in an alumina ceramic substrate as metallic conductors. In the manufacturing of a PGA packaging module, after a conventional nickel plating of Mo or W surface features is first conducted, Kovar pins are brazed onto the I/O pads with Cu--Ag or Ag as the typical brazing material. This pad/pin assembly must be protected from corrosion and wet electromigration with Ni/Au or Ni--Co/Au over--layers. For solderable modules, a thin layer of gold having a thickness between 600-1000 .ANG. is used. For pluggable modules, typically a thickness of 2 .mu.m is preferred. Additionally, the wire bond pads and the cavity die attach areas are also plated with Ni and Au to provide suitable metallurgy for Au or Ai wire bonding and Au--Si Si or JM 7000 epoxy die attach. The Au used should be 99.99% pure and conform to MIL. SPEC. 4520-C.
A key challenge in meeting the cost/performance requirements in packaging technology is to provide high density multi-layer interconnection capability with smaller wire bond pad spacing and smaller conductor widths while retaining the design flexibility to lower impedance to output pins. Electroless plating technology offers some unique advantages for the metallization of such structures. Since it does not require the ceramic circuitry to be shorted for electrical connection, it is unnecessary to have extra conductor lines routed to the edge of the substrate. This significantly simplifies the layout, reduces cross-talk due to extra conductor lines and eliminates the need to cut, grind and polish the laminated structures.
Despite the advantages offered by the electroless plating technology, the process is not necessarily suitable for all substrate materials. For instance, in recent years, with the development of high performance and high wattage chips, substrate materials that have higher capacity for heat dissipation such as aluminum nitride (AIN) have become more attractive materials. However, AIN is sensitive to highly alkaline electroless Au plating solutions. It has been determined that AIN is incompatible with solutions that have a pH above 9. While certain electroless Au processes based on sulfite plating solution chemistry operate at pH levels below 9 and are commercially available, these processes were found to provide poor quality of gold metallurgy and furthermore, building sufficiently thick deposits of between 1-2 .mu.m Au with good adhesion was not possible due to the extremely low plating rates after the initial deposition of Au associated with Ni dissolution. Most electrolytic Au plating processes work at pH levels below 9 and provide excellent quality of metallurgy. It is highly desirable to have an electrolytic plating process that retains the advantages of design flexibility and also eliminates the need for bus bars and cutting, grinding and polishing operations.
Earlier works on the development of electroplating technology for the fabrication of ceramic packages are based on extending the conductor lines to the edge of the substrate, application of conducting pastes or bending the pins so that electrical contact could be made using metal strips and/or bars. For instance, see R. Sisolak, Electronics 9 (1983) p. 25. Other workers, for instance, Fulinara et al, in U.S. Pat. No. 4,914,813 describe a method in which the metal conductor lines are extended to the sides. These lines are interconnected by applying a conductive Ag-acrylic paste to the outer edges of the substrate to provide electrical connection common to all the bond paths, cavity die area and the pins. However, this method not only increases process complexity but also does not address the cross-talk problems due to extra lines. Johnson, et al, U.S. Pat. No. 4,508,611 discloses a method that is based on bending the lead frames so that they can be mounted on a conducting moving belt. This technique applies specifically to lead frame applications and cannot be used for PGA packages. King, et al, U.S. Pat. No. 3,719,566 discloses a process for plating wire bond and I/O pads in a flat ceramic package. The method involves fabricating a glass ceramic seal and then plating the uncovered area. Electrical contact is made by a frame that is bent on the sides and pressed against the pads. The design of a jig for plating PGA has been disclosed by Roll et al. in U.S. Pat. No. 5,087,331. In his method, the pins are pre-bent in a pre-bending jig and then clipped onto a receiving jig. Electrical contact with all the pins is made by means of round or wedge-shaped metal bars or pegs clamped between pins. The bars/pegs are mounted on a metal plate arranged at right angles to the pins. The jig cannot be used with PGA modules that have unbent pins.
It is therefore an object of the present invention to provide an apparatus and method for electroplating PGA packaging modules that does not have the drawbacks of the prior art methods.
It is another object of the present invention to provide an apparatus and method for electroplating PGA packaging modules that provides high density multi-layer interconnection capability with smaller wire bond pad spacing and smaller conductor width.
It is a further object of the present invention to provide an apparatus and method for electroplating PGA packaging modules that provides smaller conductor width while retaining the design flexibility to lower the impedance to output pins.
It is another further object of the present invention to provide an apparatus and method for electroplating PGA packaging modules that allows design flexibility and simplification of the circuit layout.
It is yet another object of the present invention to provide an apparatus and method for electroplating PGA packaging modules that retains design flexibility and eliminates the need for bus bars and the cutting, grinding and polishing operations.
It is yet another further object of the present invention to provide an apparatus and method for electroplating PGA packaging modules that meets the challenge in cost/performance requirements in packaging technology for semiconductor chips.
It is still another object of the present invention to provide an apparatus and method for electroplating PGA packaging modules including cavity PGA modules and non-cavity PGA modules by utilizing a compressible member and an electrically conductive foil to provide electrical connection to the pins.